(a) Field of the Invention
The present invention concerns a semiconductor circuit device which is operated with low power dissipation and at a high speed, and more particularly it pertains to a semiconductor circuit device including an injector transistor for supplying a current and an inverter transistor for performing a switching action by a current supplied from the injector transistor.
(b) Description of the Prior Art
Integrated injection logic (referred to as IIL, hereinafter), has attracted attention ever since it has been proposed, because of the features of high speed operation and low power dissipation. An IIL circuit, fundamentally, comprises a plurality of inverter stages, each comprising an injector transistor for supplying a constant current and an inverter transistor having a control electrode means whose potential is controlled by the current supplied from the injector transistor. The output terminal of one stage is connected to the control electrode of the inverter transistor of the succeeding stage. The current supplied by an injector transistor constitutes a controlling current for the inverter transistor of the same stage, or alternatively it can constitute a main current of the inverter transistor of the preceding stage. Namely, a logic (inverter) operation is carried out by the switching-over action so that the flow of the injection current to the inverter transistor of the preceding stage is switched over to the inverter transistor of said same stage, and vice versa (between the main current of the inverter of the preceding stage and the control current of the inverter of the same stage). Thus, an IIL features the performance of switch-over between the constant-current recipient circuits, and the product of power dissipation and signal transfer delay time is advantageously small.
However, it is usual in an inverter transistor that the level of its main current is different from the level of its control current. The main current is usually much larger than the control current. A large control current enables the inverter transistor to effect a quick switching action. When the inverter transistor is turned on, however, the supply of the constant injection current will cause the problem of an excess injection. Such excess injection will cause the storage of minority carriers in the semiconductor region held at the ground potential, and will constitute a factor of limiting the operation speed.
The IIL circuit was first proposed as an improved bipolar logic. Improved IIL type logic circuit utilizing unipolar transistors have also been proposed. The unipolar transistor includes static induction transistor (hereinafter referred to as SIT) and field effect transistor (hereinafter referred to as FET), both of which may be of the junction-gate type or the insulated-gate type. The difference between the control current level and the main current level in a unipolar transistor is much greater than that noted in a bipolar transistor. Therefore, when an injector transistor supplies a current to a control electrode of a turned-on junction-gate type unipolar transistor of the same stage, an excessive charge carriers are forcibly injected from the control electrode into the semiconductor region connected to the reference voltage. Accordingly, the effect of the injected minority carriers is too great to be permissible and is one of the primary factors limiting the maximum operation speed.
Description will be made, hereinbelow, mainly on IIL-type semiconductor circuit devices employing unipolar transistors, and particularly on those employing SIT's to serve as the inverter transistors.
A static induction transistor is a unipolar transistor proposed by one (Nishizawa) of the present inventors, and has a very short channel length and a very low impurity concentration in the channel region. The channel region is easily depleted by the gate potential due to the very low impurity concentration. A potential barrier can be established in the depleted channel region and can be controlled by both of the gate potential and the drain potential. The very short channel length makes the current versus voltage characteristic unsaturating and makes the gate capacitance very small. The non-saturating characteristic provides for a low output impedance. In such an SIT potential distribution in the channel region has a focusing effect on the travelling majority carriers, and the negative temperature dependency of carrier mobility serves to prevent the thermal run-aways. Current control is achieved not by the control current but by the control of the potential barrier established in the channel, and a high input impedance is derived.
The SIT which has a high input impedance and allows direct coupling to a subsequent stage and hardly requires a driving power, and has a small power dissipation, and exhibits a non-saturating type current versus voltage characteristic and has a large transconductance and allows a large number of fan-out to be taken out, and operates at a high speed, is very suitable for being used in integrated circuits. A static induction transistor integrated circuit, which is constructed in the form of a circuit equivalent to an IIL, containing an upside-down type SIT has been proposed by one of the inventors of the present application in, for example, U.S. Ser. Nos. 748,292 and 819,343. An equivalent circuit of the basic circuitry of such SIT-IC is as shown in FIG. 1A. An example of the structure of such SIT-IC is as shown in FIG. 1B. The device shown in these Figures represents an instance of one input and two outputs.
In FIG. 1B, p.sup.+ type regions 1 and 2 represent an emitter region and a collector region, respectively, of a lateral bipolar transistor which operates as an injector. The p.sup.+ type region 2 concurrently serves as a gate region of an upside-down type SIT. Numeral 3 represents a source region of this SIT, and is formed either of an n.sup.+ type substrate or of an n.sup.+ type embedded region. Shallow n.sup.+ type regions 5 and 5' represent drains of said SIT.
An n.sup.- type continuous region partly forms a base region of the lateral bipolar transistor and partly forms a channel region of the SIT. The gate-to-gate distance or the channel width of this SIT is so selected that the channel is sufficiently pinched off by the depletion layer when no bias voltage is applied to the gate (input terminal). The lateral bipolar transistor may have a totally depleted base region to form a punching-through bipolar transistor, but preferably has a saturated characteristic. Prevention of punching-through can be achieved by separating the emitter-to-collector distance, or by increasing the impurity concentration of the base region by selective diffusion or implantation.
By the use of four masking and by relying on a standard process of diffusion technique, a power.delay product of 0.002 pJ in the low current region and a minimum delay time of 4-5 nsec at a power dissipation of about 100 .mu.W can be obtained. The minimum delay time of an SIT-IC which is manufactured by relying on a standard manufacturing process gives a value surpassing those values exhibited by VIL (Vertical Injection Logic) and SSL (Self-Aligned Super Injection Logic) which represent modified IIL. From the fact that the power.delay product is 0.07 pJ in VIL and 0.06 pJ in SSL, the power.delay product of 0.002 pJ exhibited by said SIT-IC from the standard process is noted to be as small as 1/30 or even lower than that of VIL and SSL. Such excellent abilities as shown above are attributable to the facts such as: that the current amplification factor (emitter efficiency) of the lateral bipolar transistor can be made relatively large; that the gate capacitance can be made small without increasing the gate resistance; and that the SIT has the function of focusing the carrier currents also in an upside-down type structure whose drain region has an area smaller than that of the source region, leading to a large transconductance. The factor which has limited to the operation speed of known SIT-IC is the storage effect of the excessive minority carriers injected from the gate region of an SIT which operates as an inverter into the channel region and to that surface of the substrate located on the outside of the gate region. Since an SIT, fundamentally, is a voltage controlled device, it can be turned to the conducting state even without the presence of injection of carriers from its gate region. Needless to say, an appropriate amount of minority carrier injection from the gate region can urge the injection of majority carriers from the source region to thereby minimize the resistance value of the transistor during its conducting state, allowing a large current to flow even if the channel has a small area, resulting in an improvement in the switching speed thereof. If, however, an excessive amount of minority carriers is injected, the storage effect of minority carriers around the gate region due to the IC structure using such SIT will contribute to lower the operating speed of such integrated circuit.
The storage of minority carriers within the channel region serves to lower the resistance value of the transistor in its conducting stage, and moreover the amount of minority carriers stored is small, so that an optimum design of transistor is logically possible. It should be noted, however, that in the region located outside the gate region 2 in the plan view of FIG. 1B, and also in the region located between the gate region 2 and the n.sup.+ type region 3 in the sectional view of FIG. 1B, an amount of minority carriers is stored which is greater than that stored within the channel region. For this reason, when it is intended to drive an SIT from its conducting state into its cut-off state by another SIT, the above-said large amount of minority carriers which is stored in those regions located outside the channel region should be absorbed away, and therefore the operating speed of the integrated circuit will naturally become markedly lowered. In known IIL, the driver transistor also has been formed with a bipolar transistor, and it has been considered as unavoidable from the viewpoint of operation that a very small amount of storage of minority carriers occur in the regions located outside and below the base region which corresponds to the gate region of an SIT. An excessive amount of minority carriers, however, is preferably avoided. Where the driver transistor is formed with either an SIT or FET, the elimination of this storage of minority carriers, which may be considered as only a secondary phenomenon so to speak, is of the nature of being unharmful when considered from the principles of operation. In other words, the elimination of the minority carrier storage contributes greatly to the enhancement of the speed of operation.